We are looking for Analog Layout Engineers!

Requirements:

• RTL Design experience
• STA timing constrains experience.
• Understand CMOS logic circuits.
• Should be able to perform IP layout development and physical verification activities for complex designs as per provided specifications.
• Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.
• Should have adequate knowledge of schematics, interface with circuit designer and CAD team.
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
• Excellent in problem-solving skills in solving area, power, performance and physical verification of custom layout.
• Excellent communication in English

It is not necessary to meet all the requirements, if you have basic knowledge in some points of the stack and want to enter the semiconductor industry or continue your career in the same and are excited to keep learning, do not hesitate to apply!

We have a place for everyone!